Integrated circuit memory devices such as DRAM devices are widely used in consumer and industrial products. As is well known to those having skill in the art, integrated circuit memory devices include an array of memory cells that are generally arranged in rows and columns. It will be understood that as used herein, rows and columns are used to identify relative directions in an array of memory cells rather than an absolute horizontal or vertical direction. Data is written into and read from selected memory cells using peripheral circuits including decoders and control circuits. The array of memory cells may also be arranged in a plurality of subarray blocks, each having rows and columns.
As the integration density and speed of integrated circuit memory devices continue to increase, efforts have been made to decrease the size of the individual memory cells. Moreover, efforts have also been made to more efficiently lay out or arrange the peripheral circuits in the integrated circuit, so that more of the integrated circuit area may be occupied by memory cells rather than peripheral circuits.
As the integration density of integrated circuit memory devices continues to increase, for example from 256 Kb to 256 Mb and 1 Gb or more, the number of input/output pads may also increase. As is well known to those having skill in the art, integrated circuit memory devices include input/output pads that carry input/output signals including but not limited to power supply, ground, address, data and control signals. Moreover, multibit memory devices are also being produced which may also increase the number of input/output pads. Accordingly, it is desirable to efficiently place the pads on a face of an integrated circuit substrate.
One conventional technique for locating pads on an integrated circuit memory device substrate is described in U.S. Pat. No. 5,109,265 to Utesch et al. entitled "Semiconductor Memory With Connection Pads Disposed in the Interior". FIG. 1 is a reproduction of FIG. 2 of the Utesch et al. patent. As described in the Utesch et al. patent at Column 3, line 29-51, FIG. 1 is a plan view of a semiconductor memory chip. The chip is a 64-megabyte semiconductor memory chip, in which four combined cell field blocks 10 are disposed on the comers of the chip surface 1. Within one combined cell field block 10, four single cell field blocks 8 are disposed rectangularly, with each of the single cell field blocks 8 corresponding to one cell field block 8 of the 16-megabyte semiconductor chip. One driver stage 9 is disposed between each two single cell field blocks 8 inside and parallel to the longer side of a combined cell field block 10. The driver stage 9 amplifies the signals of the word lines of the single cell field blocks 8. The decoder blocks 2, 3 are again disposed on the opposite edges of each two combined cell field blocks 10, but the word decoder blocks 2 do not form a coherent block. In this case, the free surface area 4 that can be used for the peripheral circuit blocks 11, is located only between the decoder blocks 2, 3. The connection paths or pads 5 are disposed inside the free surface area 4, parallel to the word decoders 2 and/or parallel to the bit decoder blocks 3.
Unfortunately, as shown in FIG. 1, some of the pads 5 are disposed between facing decoder blocks 2, which may increase the shorter dimension of the integrated circuit. Moreover, since the pads 5 are disposed in a line between the opposite decoder blocks 2 and 3, it may be difficult to effectively arrange the pads in an integrated circuit memory device.